1. Field of the Invention
The present invention relates to a semiconductor memory, particularly, to a data output path of a semiconductor memory. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for a semiconductor memory device for reducing parasitic capacitance or resistance of the I/O line.
2. Discussion of the Related Art
An I/O (input/output) line transferring data signals that is amplified by a bit line sense amplifier located outside of a cell array has to send the data signals to a specific data output pad, thereby resulting in a long path that reduces its operating speed. Thus, a method of arranging an I/O line to reduce parasitic capacitance or resistance of the I/O line is required.
A method of making the I/O line having a hierarchical structure is widely used for the arrangement of the I/O line. In the hierarchical structure of the I/O line, a path from a memory cell to a data output buffer is hierarchic and a data signal is amplified gradually by placing a sense amplifier at each hierarchy.
Namely, the I/O line having the hierarchical structure amplifies the data signal, which has been amplified by the bit line sense amplifier, through the I/O line and an I/O line sense amplifier, and then amplifies an output of the I/O line sense amplifier again through a data bus and a data bus sense amplifier.
FIG. 1 shows a block diagram of a semiconductor memory according to a related art, specifically illustrating the hierarchically structured I/O line, explained in the above description.
The related art shown in FIG. 1 is disclosed in U.S. Pat. No. 5,657,265 (FIG. 2) which is hereby incorporated by reference in its entirety. The construction of FIG. 1 will be explained in the following description by referring to the contents taught by U.S. Pat. No. 5,657,265.
Referring to FIG. 1, a semiconductor memory of the related art includes a plurality of memory cell array blocks 200. Each row decoder 30, formed between two memory cell array blocks, controls a word line of a memory cell array block. A column decoder 40 is arranged respectively to the central direction of a memory cell array block chip to limit a maximum length of a data path of an I/O line 7 arranged vertically. A pair of memory cell array blocks 200 adjacent to each other are arranged near about the center of the chip so that they co-own at least a row decoder 30. Each of the memory cell array blocks 200 confronting each other at the center of the chip has an independent data output pad.
An I/O switch/driver 8 connected to the respective I/O lines comprises a switch device enabled during reading data and an I/O driver enabled during writing data. The I/O switch/drivers 8 formed at corresponding places of the memory cell array blocks confronting each other are connected to a first data line 20. The first data line 20 is connected to a data sense amplifier 9, which is connected to a data I/O buffer/output pad 10. In order to read or write data simultaneously, a semiconductor memory, such as a synchronous DRAM, pursuing high data transmission bandwidth requires a memory cell array with increased number of I/O lines. As a result, the number of I/O control circuits such as I/O sense amplifiers and I/O drivers are increased in accordance with the increase in the number of I/O lines.
In the such a semiconductor memory according to the related art, data signals outputted from at least four memory cell array blocks are transferred to a data sense amplifier through at least four I/O switches and drivers and a data line, which minimizes the data input/output difference between the I/O switch and the I/O driver. However, the load on the data line is too much since the outputs from the at least four I/O switches and I/O drivers are transferred through the one data line to the data sense amplifier.
Further, the long data line connecting the respective I/O drivers to the output buffer/pad results in increased load. As a result, high speed operation of a semiconductor memory may be prevented since excessive amount of data which requires overtime for driving the data line is loaded on the data line.